LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY adder1 IS
PORT(
  a,b:IN STD_LOGIC;
  cin:IN STD_LOGIC;
  s:OUT STD_LOGIC;
  cout:OUT STD_LOGIC);
END adder1; 
ARCHITECTURE adder1p OF adder1 IS
SIGNAL h:STD_LOGIC;
  BEGIN
    h<=a XOR b;
    s<=h XOR cin;
    cout<=(a AND b) OR (h AND cin);
END adder1p;





